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the information in this document is subject to change without notice. mos integrated circuit m mm m pd16675a 1/34, 1/36 duty lcd controller/driver document no. s11195ej1v0ds00 (1st edition) date published july 1998 ns cp (k) printed in japan data sheet 1996 the m pd16675a is a driver containing a ram capable of full-dot lcd display. a single m pd16675a ic chip can operate a full-dot (up to 128-by-32 dots) lcd and two-line (upper & lower) pictograph display. this ic is ideal for kanji character or chinese character pagers, displaying 16-by-16 dots per character. features ? l cd driver with built-in display ram ? can operate on a single 3-v power supply ? booster circuit incorporated: switchable between 2x & 3x ? dot display ram: 128 32 bits ? pictographic display ram (portion of two lines): 128 2 bits ? pictographic display ram duty changeable: 1/34 and 2/36 duties ? output: 128 segments & 34 commons ? data input based on serial & 4-/8-bit parallel switchover ? split resistor incorporated ? oscillation circuit incorporated ordering information part number pa ck age m pd16675ap/w chip s /wafer (mat c hed cog mounting) m pd16675an-051 2- s ide s tandard tcp (output olb: 0.25 mm pit c h) m pd16675an- xx x tcp (tab) purchasin g the above products in terms of chips per wafer requires an exchange of other documents as well, includin g a memorandum on the produc t quality . therefore, those wh o are intereste d in this regar d are advised to contact an nec sales representative for further details.
2 m m m m pd166 75 a block diagram da cha v cha vext v lcd common driver 34 bits register segment driver 128 bits latch 128 128 34 88 seg 1 seg 128 pcom 1 ,pcom 2 com 1 com 32 osc bri pocout sync clkout lcd voltage controller osc in osc out stb e / sck ws cs 0 cs 1 cs 2 d 7 / ns d 6 / cae d 5 d 4 d 3 d 2 d 1 d 0 / data c 1 c 1 c 2 c 2 v lc5 v lc4 v lc3 v lc2 v lc1 amp in ( ) amp in ( ) lcd timing controller dc / dc converter read / write controller clock buffer clock 8 blink controller cpu interface command / data controller display mode reg. mode reg. command decoder 88 memory data pointer a0-a7 address controller 8 8 8 8 8 8 8 8 pict data memory (128 1 bits) blink data memory (128 1 bits) data memory bank 0 (128 8 bits) data memory bank 1 (128 8 bits) data memory bank 2 (128 8 bits) data memory bank 3 (128 8 bits) pict data memory (128 1 bits) blink data memory (128 1 bits) read/write buffer
3 m m m m pd166 75 a pin configuration (pad layout) (chip size: 12.68 1.81 mm 2 ) 1 13 158 146 245 159 145 14 x y no. pin x ( m m ) y ( m m ) 1 dummy -6094.8 516.6 2 dummy -6094.8 426.6 3com 22 -6094.8 336.6 4com 21 -6094.8 246.6 5com 20 -6094.8 156.6 6com 19 -6094.8 66.6 7com 18 -6094.8 -23.4 8com 17 -6094.8 -113.4 9 dummy -6094.8 -203.4 10 dummy -6094.8 -293.4 11 dummy -6094.8 -383.4 12 dummy -6094.8 -473.4 13 dummy -6094.8 -563.4 14 dummy -5893.8 -661.6 15 dummy -5803.8 -661.6 16 seg 128 -5713.8 -661.6 17 seg 127 -5623.8 -661.6 18 seg 126 -5533.8 -661.6 19 seg 125 -5443.8 -661.6 20 seg 124 -5353.8 -661.6 21 seg 123 -5263.8 -661.6 22 seg 122 -5173.8 -661.6 23 seg 121 -5083.8 -661.6 24 seg 120 -4993.8 -661.6 25 seg 119 -4903.8 -661.6 26 seg 118 -4813.8 -661.6 27 seg 117 -4723.8 -661.6 28 seg 116 -4633.8 -661.6 29 seg 115 -4543.8 -661.6 30 seg 114 -4453.8 -661.6 31 seg 113 -4363.8 -661.6 32 seg 112 -4273.8 -661.6 33 seg 111 -4183.8 -661.6 34 seg 110 -4093.8 -661.6 35 seg 109 -4003.8 -661.6 36 seg 108 -3913.8 -661.6 37 seg 107 -3823.8 -661.6 38 seg 106 -3733.8 -661.6 39 seg 105 -3643.8 -661.6 40 seg 104 -3553.8 -661.6 41 seg 103 -3463.8 -661.6 42 seg 102 -3373.8 -661.6 43 seg 101 -3283.8 -661.6 44 seg 100 -3193.8 -661.6 45 seg 99 -3103.8 -661.6 46 seg 98 -3013.8 -661.6 47 seg 97 -2923.8 -661.6 48 seg 96 -2833.8 -661.6 49 seg 95 -2743.8 -661.6 50 seg 94 -2653.8 -661.6 51 seg 93 -2563.8 -661.6 52 seg 92 -2473.8 -661.6 53 seg 91 -2383.8 -661.6 54 seg 90 -2293.8 -661.6 55 seg 89 -2203.8 -661.6 56 seg 88 -2113.8 -661.6 57 seg 87 -2023.8 -661.6 58 seg 86 -1933.8 -661.6 59 seg 85 -1843.8 -661.6 60 seg 84 -1753.8 -661.6 61 seg 83 -1663.8 -661.6 62 seg 82 -1573.8 -661.6 63 seg 81 -1483.8 -661.6 no. pin x ( m m ) y ( m m ) 64 seg 80 -1393.8 -661.6 65 seg 79 -1303.8 -661.6 66 seg 78 -1213.8 -661.6 67 seg 77 -1123.8 -661.6 68 seg 76 -1033.8 -661.6 69 seg 75 -943.8 -661.6 70 seg 74 -853.8 -661.6 71 seg 73 -763.8 -661.6 72 seg 72 -673.8 -661.6 73 seg 71 -583.8 -661.6 74 seg 70 -493.8 -661.6 75 seg 69 -403.8 -661.6 76 seg 68 -313.8 -661.6 77 seg 67 -223.8 -661.6 78 seg 66 -133.8 -661.6 79 seg 65 -43.8 -661.6 80 seg 64 46.2 -661.6 81 seg 63 136.2 -661.6 82 seg 62 226.2 -661.6 83 seg 61 316.2 -661.6 84 seg 60 406.2 -661.6 85 seg 59 496.2 -661.6 86 seg 58 586.2 -661.6 87 seg 57 676.2 -661.6 88 seg 56 766.2 -661.6 89 seg 55 856.2 -661.6 90 seg 54 946.2 -661.6 91 seg 53 1036.2 -661.6 92 seg 52 1126.2 -661.6 93 seg 51 1216.2 -661.6 94 seg 50 1306.2 -661.6 95 seg 49 1396.2 -661.6 96 seg 48 1486.2 -661.6 97 seg 47 1576.2 -661.6 98 seg 46 1666.2 -661.6 99 seg 45 1756.2 -661.6 100 seg 44 1846.2 -661.6 101 seg 43 1936.2 -661.6 102 seg 42 2026.2 -661.6 103 seg 41 2116.2 -661.6 104 seg 40 2206.2 -661.6 105 seg 39 2296.2 -661.6 106 seg 38 2386.2 -661.6 107 seg 37 2476.2 -661.6 108 seg 36 2566.2 -661.6 109 seg 35 2656.2 -661.6 110 seg 34 2746.2 -661.6 111 seg 33 2836.2 -661.6 112 seg 32 2926.2 -661.6 113 seg 31 3016.2 -661.6 114 seg 30 3106.2 -661.6 115 seg 29 3196.2 -661.6 116 seg 28 3286.2 -661.6 117 seg 27 3376.2 -661.6 118 seg 26 3466.2 -661.6 119 seg 25 3556.2 -661.6 120 seg 24 3646.2 -661.6 121 seg 23 3736.2 -661.6 122 seg 22 3826.2 -661.6 123 seg 21 3916.2 -661.6 124 seg 20 4006.2 -661.6 125 seg 19 4096.2 -661.6 126 seg 18 4186.2 -661.6 no. pin x ( m m ) y ( m m ) 127 seg 17 4276.2 -661.6 128 seg 16 4366.2 -661.6 129 seg 15 4456.2 -661.6 130 seg 14 4546.2 -661.6 131 seg 13 4636.2 -661.6 132 seg 12 4726.2 -661.6 133 seg 11 4816.2 -661.6 134 seg 10 4906.2 -661.6 135 seg 9 4996.2 -661.6 136 seg 8 5086.2 -661.6 137 seg 7 5176.2 -661.6 138 seg 6 5266.2 -661.6 139 seg 5 5356.2 -661.6 140 seg 4 5446.2 -661.6 141 seg 3 5536.2 -661.6 142 seg 2 5626.2 -661.6 143 seg 1 5716.2 -661.6 144 dummy 5806.2 -661.6 145 dummy 5896.2 -661.6 146 dummy 6094.8 -563.4 147 dummy 6094.8 -473.4 148 dummy 6094.8 -383.4 149 dummy 6094.8 -293.4 150 dummy 6094.8 -203.4 151 pcom 1 6094.8 -113.4 152 com 1 6094.8 -23.4 153 com 2 6094.8 66.6 154 com 3 6094.8 156.6 155 com 4 6094.8 246.6 156 com 5 6094.8 336.6 157 dummy 6094.8 426.6 158 dummy 6094.8 516.6 159 dummy 5870.6 760 160 dummy 5780.6 760 161 dummy 5690.6 760 162 dummy 5600.6 760 163 com 6 5510.6 760 164 com 7 5420.6 760 165 com 8 5330.6 760 166 com 9 5240.6 760 167 com 10 5150.6 760 168 com 11 5060.6 760 169 com 12 4970.6 760 170 com 13 4880.6 760 171 com 14 4790.6 760 172 com 15 4700.6 760 173 com 16 4610.6 760 174 dummy 4520.6 760 175 v lc5 4400.8 760 176 v lc4 4224.8 760 177 v lc3 4048.8 760 178 v lc2 3872.8 760 179 v lc1 3696.8 760 180 v lcd 3520.8 760 181 v lcd 3344.8 760 182 amp in ( - ) 3168.8 760 183 amp in ( + ) 2992.8 760 184 amp out 2816.8 760 185 c 1 - 2640.8 760 186 c 1 - 2550.8 760 187 c 1 - 2460.8 760 188 c 1 + 2284.8 760 189 c 1 + 2194.8 760 no. pin x ( m m ) y ( m m ) 190 c 1 + 2104.8 760 191 c 2 - 1928.8 760 192 c 2 - 1838.8 760 193 c 2 - 1748.8 760 194 c 2 + 1572.8 760 195 c 2 + 1482.8 760 196 c 2 + 1392.8 760 197 v dd2 1232.8 760 198 vext 1056.8 760 199 osc bri 880.8 760 200 osc in 704.8 760 201 osc out 528.8 760 202 da cha 352.8 760 203 v dd1 176.8 760 204 v dd1 0.8 760 205 v cha -175.2 760 206 v ss -351.2 760 207 cs 0 -527.2 760 208 cs 1 -703.2 760 209 cs 2 -879.2 760 210 reset - 1055.2 760 211 d 7 /ns -1231.2 760 212 d 6 /cae -1407.2 760 213 d 5 -1583.2 760 214 d 4 -1759.2 760 215 d 3 -1935.2 760 216 d 2 -2111.2 760 217 d 1 -2287.2 760 218 d 0 /data -2463.2 760 219 e/sck -2639.2 760 220 stb -2815.2 760 221 v ss -2991.2 760 222 v ss -3167.2 760 223 ws -3343.2 760 224 v dd1 -3519.2 760 225 pocout -3695.2 760 226 clkout -3871.2 760 227 sync -4047.2 760 228 v ee -4223.2 760 229 v ee -4399.2 760 230 dummy -4520.6 760 231 pcom 2 -4610.6 760 232 com 32 -4700.6 760 233 com 31 -4790.6 760 234 com 30 -4880.6 760 235 com 29 -4970.6 760 236 com 28 -5060.6 760 237 com 27 -5150.6 760 238 com 26 -5240.6 760 239 com 25 -5330.6 760 240 com 24 -5420.6 760 241 com 23 -5510.6 760 242 dummy -5600.6 760 243 dummy -5690.6 760 244 dummy -5780.6 760 245 dummy -5870.6 760
4 m m m m pd166 75 a contents 1. pin functions ................................................................................................................ .................... 6 1.1 power system................................................................................................................ ............................... 6 1.2 logic system................................................................................................................ ................................ 6 1.3 driver system ............................................................................................................... ................................ 8 2. voltage control circuit ...................................................................................................... ...... 8 3. lcd display .................................................................................................................. ...................... 9 4. group addresses.............................................................................................................. ............ 10 4.1 dot display ................................................................................................................. ................................ 10 4.2 pictographic display........................................................................................................ .......................... 11 4.3 blink data.................................................................................................................. .................................. 12 5. command ...................................................................................................................... ..................... 13 5.1 basic form.................................................................................................................. ................................ 13 5.2 chip address register (car) ................................................................................................. .................. 13 5.3 command register ............................................................................................................ ........................ 14 5.3.1 reset ..................................................................................................................... .......................... 14 5.3.2 display on/off ............................................................................................................ .................. 14 5.3.3 standby ................................................................................................................... ........................ 14 5.3.4 duty setting.............................................................................................................. ........................ 15 5.3.5 master/slave setting...................................................................................................... ................... 15 5.3.6 blink setting ............................................................................................................. ........................ 15 5.3.7 data r/w mode ............................................................................................................. .................. 16 5.3.8 test mode................................................................................................................. ....................... 16 5.3.9 d/a converter setting ..................................................................................................... .................. 16 5.4 address register ............................................................................................................ ........................... 17 6. resetting.................................................................................................................... ...................... 18 7. communication format ......................................................................................................... ..... 19 7.1 serial ...................................................................................................................... ..................................... 19 7.1.1 reception 1 (command/data write: 1 byte) .................................................................................. ... 19 7.1.2 reception 2 (command/data write: 2 bytes or more) ...................................................................... 19 7.1.3 transmission (command/data read) .......................................................................................... ..... 19 7.2 parallel .................................................................................................................... .................................... 20 7.2.1 8-bit parallel interface .................................................................................................. .................... 20 7.2.2 4-bit parallel interface .................................................................................................. .................... 20 8. cpu access examples .......................................................................................................... ........ 21 8.1 initialize and data write................................................................................................... .......................... 21 8.2 change display data and pictographic data (all data are changed) ................................................... 23 8.3 read display data and pictograph data ....................................................................................... ........... 24 8.4 blink data setting .......................................................................................................... ............................ 25 9. electrical characteristics ................................................................................................... .26
5 m m m m pd166 75 a 10. package drawing ............................................................................................................. .............32
6 m m m m pd166 75 a 1. pin functions 1.1 power system pin symbol pin name pin no. i/o description v dd1 logic power supply pin 203, 204, 224 --- power supply pin for logic v dd2 power supply pin for booster circuit 197 --- power supply pin for booster circuit. set the pin to v dd1 v dd2 . v ss logic ground pin 206, 221, 222 --- ground pin for logic v lcd driver power supply pin 180, 181 --- driver power supply pin. output pin of internal booster circuit. connect with a 1- m f booster capacitor to the v dd2 pin. when not using the internal booster circuit, the driver power can be turned on directly. v lc1 to v lc5 driver reference power supply 179 to 175 --- reference power supply pin for lcd drive. when the internal bias is selected, be sure to leave it open. c 1 + , c 1 - , c 2 + , c 2 - capacitor connection pins 185 to 196 --- capacitor connection pins for booster circuit. connect a 1 m f capacitor. v ee driver ground pin 228, 229 --- ground pin for driver 1.2 logic system pin symbol pin name pin no. i/o description ws word length selection 223 i this pin selects the word length. at high level, it becomes an 8-bit parallel interface. at low level, it becomes a 4-bit parallel interface if d 7 /ns is high; and a serial interface if d 7 /ns is low. when the word length is 4 bits, data is transferred in the upper- to-lower sequence by means of data buses d 0 to d 3 . the word length cannot be changed after power-on. stb strobe 220 i data can be input/output at low level either in parallel interface or serial interface mode. e/sck enable/shift clock 219 i in parallel interface mode, this becomes the data enable input pin. during read-in, data is fetched into the interface buffer at the rising edge. during read- out, data is fetched from the interface buffer at the falling edge. in serial interface mode, this pin becomes the data shift clock. during read-in, data is fetched into the shift register at the rising edge. during read-out, data is fetched from the shift register at the falling edge. clkout clock for slave ic output 226 o this pin outputs an inverted oscillation clock. it connects to slave ic s osc in directly. pocout power-on reset monitor 225 o monitor pin for internal power-on reset. at low level, power-on reset is set internally. at low level, power-on reset is released. the pin is for ic testing. normally leave it open.
7 m m m m pd166 75 a 1.2 logic system (continued) pin symbol pin name pin no. i/o description d 0 /data data bus/data 218 i/o in parallel interface mode, this pin becomes the d 0 bit of the data bus. in serial interface mode, it becomes the input/output pin of the command and display data (3 states). d 1 to d 5 data bus 217 to 213 i/o in parallel interface mode, these pins become the d 1 to d 5 bits of the data bus. in serial interface mode, leave them open. d 6 /cae data bus/chip address enable 212 i/o in 8-bit parallel interface mode, this pin becomes the d 6 bit of the data bus. in 4-bit parallel interface and serial interface modes, it becomes chip address enable. also, at high level, it becomes chip address valid; at low level, chip address invalid. in 8-bit parallel interface, it becomes chip address valid. d 7 /ns data bus/nibble select 211 i/o when the word select (ws) is high level, this bit becomes the d 7 bit of the data bus. when ws is low level, it becomes the nibble select (ns). when ns is high level, it becomes 4-bit parallel interface. when ns is low level, it becomes serial interface. in 4-bit parallel interface mode, data cannot be read out. _____________ reset reset 210 i at low level, internal initialization is performed. v cha boosting magnitude switching 205 i the boosting magnitude of the internal booster circuit is switched over. at high level, it is switched to 3x, while, at low level, 2x. da cha d/a converter switching 202 i select whether to use the internal d/a converter for temperature correction or not. at high level, this circuit is used, at low level, unused. vext reference supply switching 198 i selects the method for supplying the reference power circuit. at high level, the circuit is supplied externally; and, at low level, internally. sync synchronization 227 i/o input/output pin for synchronization. master mode: output slave mode: input cs 0 to cs 2 chip select 207 to 209 i when used for multiple chips, these pins are used to specify their addresses. they can be accessed only when coinciding with b2 to b4 bits of the interface control register. osc in oscillation pin 200 i osc out 201 o these pins are connected with the 1 m w resistor. when using external oscillation, input it into the osc in , leaving the osc out open. osc bri external clock for blinks 199 i input pin of the 2-hz external clock. it internally divides this clock by 2 to generate 1 hz and make it the synchronizing signal for blinks.
8 m m m m pd166 75 a 1.3 driver system pin symbol pin name pin no. i/o description seg 1 to seg 128 segment 143 to 16 o segment output pins com 1 to com 32 commons 3 to 8, 152 to 156, 163 to 173, 232 to 241 o common output pins pcom 1 , pcom 2 pictographic commons 151, 231 o common output pins for pictograph amp in ( + ), amp in ( - ) operational amplifier input 183, 182 i these are the input pins of the operational amplifier for lcd drive voltage adjustment. leave amp in (+) open when using the internal d/a converter. when not using the d/a converter, it is necessary to input the reference voltage. connect amp in (C) to the lcd voltage adjustment resistor (see the diagram below). amp out operational amplifier output 184 o this is the input pin of the operational amplifier for lcd drive voltage adjustment. it is normal to connect this pin to the lcd voltage adjustment resistor (see the diagram below). it is recommended to connect approx. 0.1 to 1 m f capacitor to this pin to stabilize the internal amplifiers output. 2. voltage control circuit example d/a converter da cha amp in ( ) amp in ( ) amp out v lc1 v lc2 v lc3 v lc4 v lc5 v ee vext r 2 r 1 c 1 reference power circuit
9 m m m m pd166 75 a 3. lcd display the m pd16675as lcd can display 128 by 32 dots (called full-dot display) as well as 128 by 2 pictographs on a single screen. ? ? y ? ? t pictographic display (128 pictographs) 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 seg pcom 1 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 com 18 com 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 com 32 ? ? y ? ? t pictographic display (128 pictographs) pcom 2
10 m m m m pd166 75 a 4. group addresses 4.1 dot display the group addresses of dot display are assigned as follows. if address increment is set, when the x address goes to 7fh, the next address is 00h. at this time, the y address changes to the next address. also, when the y address goes to 03h, the next address is 00h. 00h 01h 02h 03h 7eh 7fh 00h 01h 02h 03h y addresses x addresses b7 b6 b5 b4 b3 b2 b1 b0
11 m m m m pd166 75 a 4.2 pictographic display the group addresses of pictograph display are assigned as follows. if address increment is set, when the x address goes to 0fh, the next address is 00h. at this time, the y address changes to the next address. also, when the y address goes to 01h, the next address is 00h. 00h 01h 02h 03h 0eh 0fh 00h (pcom 1 ) y addresses x addresses b7 b6 b5 b4 b3 b2 b1 b0 8 bits 01h (pcom 2 ) ? ? ? ? ? ? y ? ? ? ? ? t (1) pcom 1 (y address = 00h) x address segment output no. b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 9 10111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 08h 65 66 67 68 69 70 71 72 09h 73 74 75 76 77 78 79 80 0ah 8182838485868788 0bh 8990919293949596 0ch 97 98 99 100 101 102 103 104 0dh 105 106 107 108 109 110 111 112 0eh 113 114 115 116 117 118 119 120 0fh 121 122 123 124 125 126 127 128 (2) pcom 2 (y address = 01h) x address segment output no. b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 9 10111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 08h 65 66 67 68 69 70 71 72 09h 73 74 75 76 77 78 79 80 0ah 8182838485868788 0bh 8990919293949596 0ch 97 98 99 100 101 102 103 104 0dh 105 106 107 108 109 110 111 112 0eh 113 114 115 116 117 118 119 120 0fh 121 122 123 124 125 126 127 128
12 m m m m pd166 75 a 4.3 blink data the group addresses of pictographic blink data are assigned as follows. write 1 in the address of the pictographic to be blinked. if address increment is set, when the x address goes to 0fh, the next address is 00h. at this time, the y address changes to the next address. also, when the y address goes to 01h, the next address is 00h. 00h 01h 02h 03h 0eh 0fh 00h (pcom 1 ) y addresses x addresses b7 b6 b5 b4 b3 b2 b1 b0 8 bits 01h (pcom 2 ) ? ? ? ? ? ? y ? ? ? ? ? t (1) pcom 1 (y address = 00h) x address segment output no. b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 9 10111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 08h 65 66 67 68 69 70 71 72 09h 73 74 75 76 77 78 79 80 0ah 8182838485868788 0bh 8990919293949596 0ch 97 98 99 100 101 102 103 104 0dh 105 106 107 108 109 110 111 112 0eh 113 114 115 116 117 118 119 120 0fh 121 122 123 124 125 126 127 128 (2) pcom 2 (y address = 01h) x address segment output no. b7 b6 b5 b4 b3 b2 b1 b0 00h 12345678 01h 9 10111213141516 02h 17 18 19 20 21 22 23 24 03h 25 26 27 28 29 30 31 32 04h 33 34 35 36 37 38 39 40 05h 41 42 43 44 45 46 47 48 06h 49 50 51 52 53 54 55 56 07h 57 58 59 60 61 62 63 64 08h 65 66 67 68 69 70 71 72 09h 73 74 75 76 77 78 79 80 0ah 8182838485868788 0bh 8990919293949596 0ch 97 98 99 100 101 102 103 104 0dh 105 106 107 108 109 110 111 112 0eh 113 114 115 116 117 118 119 120 0fh 121 122 123 124 125 126 127 128
13 m m m m pd166 75 a 5. command 5.1 basic form chip address register (car) ? y ? t ? y ? t command register (cr) address register (ar) + ++ x address (xad) data 1 (dt1) + data 2 (dt2) + + ? ? 5.2 chip address register (car) 00000b2b1b0 chip address 000: cs 2 = 0, cs 1 = 0, and cs o = 0 ics accessible 001: cs 2 = 0, cs 1 = 0, and cs o = 1 ics accessible 010: cs 2 = 0, cs 1 = 1, and cs o = 0 ics accessible 011: cs 2 = 0, cs 1 = 1, and cs o = 1 ics accessible 100: cs 2 = 1, cs 1 = 0, and cs o = 0 ics accessible 101: cs 2 = 1, cs 1 = 0, and cs o = 1 ics accessible 110: cs 2 = 1, cs 1 = 1, and cs o = 0 ics accessible 111: cs 2 = 1, cs 1 = 1, and cs o = 1 ics accessible msb lsb the register is made valid in the following states. interface cae high level low level serial valid invalid 4-bit parallel valid invalid 8-bit parallel valid (cae: used as the d 6 bit) it is unnecessary to transmit the register that is invalid.
14 m m m m pd166 75 a 5.3 command register the command registers basic configuration is as follows. b7 b6 b5 b4 b3 b2 b1 b0 choices msb lsb command type (0 h to b h) 5.3.1 reset all the ics commands are initialized. resetting takes effect only during the internally predetermined time (one shot). 00100111 msb lsb 5.3.2 display on/off on/off of the display is controlled. 00001b2b1b0 choices 000: lcd off (seg n , com n , pcom n = v ee ) 001: lcd off (seg n , com n , pcom n = nonselective waveform) 111: lcd on msb lsb 5.3.3 standby the dc/dc converter is stopped, thus reducing the supply current. the display is placed in the off state (seg n , com n = v ee ). 00010b2b1b0 choices 000: normal operation 001: standby (dc/dc converter halt, all display off note ) msb lsb note seg n , com n , pcom n = v ee
15 m m m m pd166 75 a 5.3.4 duty setting the duty is set. 00011b2b1b0 choices 000: 1/34 duty cycle 001: 1/36 duty cycle note msb lsb note if the duty cycle is 1/36, pcom 1 and pcom 2 are respectively selected for twice the period of the duty (2/36). 5.3.5 master/slave setting the master/slaves are set. 00111b2b1b0 choices 000: master 001: slave msb lsb 5.3.6 blink setting the blinks of the pictograph of the address whose blink data is 1 are controlled. 01000b2b1b0 choices 000: blink halt 001: blink start (blink frequency = f osc /32768) 010: blink start (blink frequency = f bri note /2) msb lsb note this refers to the frequency of the external clock which is input from the osc bri pin.
16 m m m m pd166 75 a 5.3.7 data r/w mode data read/write (r/w), increment, address counter resetting, etc. are set in this mode. 10110b2b1b0 choices 1 00: the address is incremented (+1) after being reset (x address = 00h, y address = 00h). note 1 01: the address is incremented starting from the current one. note 2 10: the address is not incremented after being reset. 11: current address retained. msb lsb choices 2 0: data writing 1: data reading note 3 notes 1. when the x address goes to the last address, the next address is 00h. 2. the data read mode is cancelled at stbs rising edge (switched to data write mode). 3. in 4-bit parallel interface mode, data cannot be read out. 5.3.8 test mode the test mode is set. the test mode is for checking ic operation, and no assurance is made for its regular use or continued operation. 10111b2b1b0 choices 000: normal operation 001 to 111: test mode msb lsb 5.3.9 d/a converter setting d/a converter output is set in 32 steps from v dd2 to 2/3 v dd2 . 1 0 0 b4 b3 b2 b1 b0 choices 00h (min.) to 1fh (max.) msb lsb 10h is set after reset.
17 m m m m pd166 75 a 5.4 address register selects the address type and specifies the address. 1 1 b5 b4 0 0 b1 b0 y address dot display group addresses pictograph group addresses blink group addresses msb lsb : 00h to 03h : 00h to 01h : 00h to 01h y t choices 00: dot address 01: pictograph group address 10: blink data group address 0 b6b5b4b3b2b1b0 msb lsb x address + caution if unspecified addresses have been set, the operation is not assured.
18 m m m m pd166 75 a 6. resetting when reset (power-on reset, command reset, hardware (terminal) reset), the contents of each register are as follows: register name register contents status b7 b6 b5 b4 b3 b2 b1 b0 chip address register 0 0 0 0 0 0 0 0 the ics of cs 2 = 0, cs 1 = 0, cs 0 = 0 can be accessed. display on/off 00001000lcd off (seg n , com n , pcom n = v lc5 ) standby 0 0 0 1 0 0 0 0 normal operation duty setting 0 0 0 1 1 0 0 0 1/34 duty cycle blink setting 01000000blink halt d/a converter setting 1 0 0 0 0 0 0 0 lcd drive voltage: set to 2/3 v dd2 data r/w mode 1 0 1 1 0 0 0 0 data write/address reset/increment (+1) test mode 1 0 1 1 1 0 0 0 normal operation
19 m m m m pd166 75 a 7. communication format 7.1 serial 7.1.1 reception 1 (command/data write: 1 byte) 1 2 3 b7 b6 b5 678 b2 b1 b0 stb data sck 7.1.2 reception 2 (command/data write: 2 bytes or more) b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 123 678 12345 command 1 wait time t wait command 1/data str data sck 7.1.3 transmission (command/data read) b7 b6 b5 b2 b1 b0 b7 b6 b5 b4 b3 123 678 123456 data read command setting wait time t wait data read str data sck
20 m m m m pd166 75 a 7.2 parallel 7.2.1 8-bit parallel interface stb d 0 to d 7 e 7.2.2 4-bit parallel interface higher lower higher lower higher lower stb d 0 to d 7 e
21 m m m m pd166 75 a 8. cpu access examples examples of access procedure are shown below. in serial or 4-bit parallel interface mode, the chip address register (car) is not transmitted when the car is invalid (cae = l, see page 13). 8.1 initialize and data write parameter stb command/data description b7 b6 b5 b4 b3 b2 b1 b0 start h xxxxxxxx (power-on reset is released 200 m s after power supply is started) chip address register (car) l 00000000 chip address = 000 duty setting l 00011000 1/34 duty h xxxxxxxx car l 00000000 chip address = 000 d/a converter setting l 10010000 d/a converter output = 10000h h xxxxxxxx car l 00000000 chip address = 000 address register 1 l 11000000 dot address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 data r/w mode l 10110001 data write, the address is incremented starting from the current one. dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 02h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 03h (128 bytes) h xxxxxxxx car l 00000000 chip address = 000 address register 1 l 11010000 pictogr aph group address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 remark x = don't care, d = data
22 m m m m pd166 75 a 8.1 initialize and data write (continued) parameter stb command/data description b7 b6 b5 b4 b3 b2 b1 b0 data r/w mode l 10110001 data write, the address is incremented starting from the current one. pict display data 1 | pict display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (16 bytes) pict display data 1 | pict display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (16 bytes) h xxxxxxxx car l 00000000 chip address = 000 display on/off l 00001111 lcd on end h xxxxxxxx remark x = don't care, d = data
23 m m m m pd166 75 a 8.2 change display data and pictographic data (all data are changed) parameter stb command/data description b7 b6 b5 b4 b3 b2 b1 b0 start h xxxxxxxx chip address register (car) l 00000000 chip address = 000 address register 1 l 11000000 dot address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 data r/w mode l 10110001 data write, the address is incremented starting from the current one. dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 02h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 03h (128 bytes) h xxxxxxxx car l 00000000 chip address = 000 address register 1 l 11010000 pictogr aph group address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 data r/w mode l 10110001 data write, the address is incremented starting from the current one. pict display data 1 | pict display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (16 bytes) pict display data 1 | pict display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (16 bytes) end h xxxxxxxx remark x = don't care, d = data
24 m m m m pd166 75 a 8.3 read display data and pictograph data parameter stb command/data description b7 b6 b5 b4 b3 b2 b1 b0 start h xxxxxxxx chip address register (car) l 00000000 chip address = 000 address register 1 l 11000000 dot address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 data r/w mode l 10110101 data write, the address is incremented starting from the current one. dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 02h (128 bytes) dot display data 1 | dot display data 128 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 03h (128 bytes) h xxxxxxxx car l 00000000 chip address = 000 address register 1 l 11010000 pictogr aph group address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 data r/w mode l 10110101 data write, the address is incremented starting from the current one. pict display data 1 | pict display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (16 bytes) h xxxxxxxx pict display data 1 | pict display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (16 bytes) end h xxxxxxxx remark x = don't care, d = data
25 m m m m pd166 75 a 8.4 blink data setting parameter stb command/data description b7 b6 b5 b4 b3 b2 b1 b0 start h xxxxxxxx chip address register (car) l 00000000 chip address = 000 address register 1 l 11100000 blink data gr oup address, y address = 00h address register 2 l 00000000 x address = 00h h xxxxxxxx car l 00000000 chip address = 000 data r/w mode l 10110001 data write, the address is incremented starting from the current one. blink display data 1 | blink display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 00h (16 bytes) blink display data 1 | blink display data 16 l | l d d d d d d d d d d d d d d d d ? y ? t data of y address = 01h (16 bytes) h xxxxxxxx car l 00000000 chip address = 000 blink setting l 01000010 start blinking, blink fr equency = f bri /2 end h xxxxxxxx remark x = don't care, d = data
26 m m m m pd166 75 a 9. electrical characteristics absolute maximum ratings (t a = + + + + 25 c, v ss = v ee = 0 v) parameter symbol rating unit logic supply voltage v dd1 - 0.3 to + 7.0 v booster circuit supply voltage (v cha = h) v dd2 - 0.3 to + 5.0, v dd1 v dd2 v booster circuit supply voltage (v cha = l) v dd2 - 0.3 to + 7.0, v dd1 v dd2 v driver supply voltage v lcd - 0.3 to + 15.0, v dd2 v lcd v driver reference supply input voltage v lc1 to v lc5 - 0.3 to v lcd + 0.3 v logic system i nput voltage v in1 - 0.3 to v dd1 + 0.3 v logic system output voltage v out1 - 0.3 to v dd1 + 0.3 v logic system i nput/output voltage v i/o1 - 0.3 to v dd1 + 0.3 v driver system i nput voltage v in2 - 0.3 to v lcd + 0.3 v driver system output voltage v out2 - 0.3 to + v lcd + 0.3 v operating temperature t a - 40 to + 85 c storage temperature t stg - 55 to + 150 c caution if the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. be sure to use the product within the range of the absolute maximum ratings. recommended operating range parameter symbol min. typ. max. unit logic supply voltage v dd1 note 1 2.7 3.3 v booster circuit supply voltage (v cha = h) v dd2 note 1 2.7 3.0 3.6 v booster circuit supply voltage (v cha = l) v dd2 note 1 2.7 5.0 5.5 v driver supply voltage v lcd note 2 v dd2 10 12 v logic system i nput voltage v in 0v dd1 v driver system i nput voltage v lc1 to v lc5 0v lcd v notes 1. set this to v dd1 v dd2 . 2. if use external lcd voltage as v lcd , cannot use standby. also, maintain v dd1 = v dd2 . caution at power on and power off, keep v dd1 v dd2 v lcd .
27 m m m m pd166 75 a electrical specifications (unless otherwise specified, t a = - - - - 40 to + + + + 85 c, v dd1 = 2.7 to 3.3 v, v cha = h: v dd2 = 2.7 to 3.6 v or v cha = l: v dd2 = 2.7 to 5.5 v) parameter symbol condition min. typ. max. unit high level input voltage v ih 0.8 v dd1 v low level input voltage v il 0.2 v dd1 v high level input current i ih1 except d 0 /data, d 1 to d 7 /ns, da cha 1 m a low level input current i il1 except d 0 /data, d 1 to d 7 /ns, da cha - 1 m a high level output voltage v oh i out = - 1.5 ma, except osc out v dd1 - 0.5 v low level output voltage v ol i out = 4 ma, except osc out 0.5 v high level leakage current i loh d 0 /data, d 1 to d 7 /ns v in/out = v dd1 10 m a low level leakage current i lol d 0 /data, d 1 to d 7 /ns v in/out = v ss - 10 m a common output on resistance r com v lcn ? com n , v lcd 3 2 v dd2 |i o | = 50 m a 2k w segment output on resistance r seg v lcn ? seg n , v lcd 3 2 v dd2 |i o | = 50 m a 4k w v lcd v cha = l, note 1.8 v dd2 2.0 v dd2 v driver supply voltage (booster voltage) v cha = h, note 2.7 v dd2 3.0 v dd2 v logic system current consumption (v dd1 ) i dd11 f osc = 30 khz, no load v dd1 = v dd2 = 3.0 v, not to access ram 30 m a f osc = 30 khz, no load v dd1 = v dd2 = 3.0 v, to access ram 60 m a driver system current consumption (v dd2 ) i dd21 f osc = 30 khz, all display off data output, v dd1 = v dd2 = 3.0 v, vcha = h, note 150 m a remark the typ. value is a reference value when t a = 25 c. note measurement circuit da cha + - amp in ( + ) d/a converter reference power circuit amp out amp in ( - ) v dd1 v lc1 v lc2 v lc3 v lc4 v lc5 v ee vext
28 m m m m pd166 75 a switching characteristics (unless otherwise specified, t a = - - - - 40 to + + + + 85 c, v dd1 = 2.7 to 3.3 v, v cha = h: v dd2 = 2.7 to 3.6 v or v cha = l: v dd2 = 2.7 to 5.5 v) parameter symbol condition min. typ. max. unit oscillation frequency f osc self-oscillation 21 30 50 khz transfer delay time t phl sck ? data 100 ns t plh sck ? data - 300 ns remark the typ. value is a reference value when t a = 25 c. the time for one frame is obtained with the following formula. 1 frame = 1/f osc 8 number of duties if f osc = 30 khz and 1/34 duty, then the result is: 1 frame = 33 m s 8 34 = 9.1 ms required conditions for timing (unless otherwise specified, t a = - - - - 40 to + + + + 85 c, v dd1 = 2.7 to 3.3 v, v cha = h: v dd2 = 2.7 to 3.6 v or v cha = l: v dd2 = 2.7 to 5.5 v) (1) common parameter symbol condition min. typ. max. unit clock frequency f osc osc in external clock 20 30 50 khz high level clock pulse width t whc1 osc in external clock 10 25 m s low level clock pulse width t wlc1 osc in external clock 10 25 m s high level clock pulse width t whc2 osc bri external clock 400 ns low level clock pulse width t wlc2 osc bri external clock 400 ns rise/fall time t r , t f osc bri external clock 100 ns reset pulse width t wre reset pin 1.0 m s remark the typ. value is a reference value when t a = 25 c.
29 m m m m pd166 75 a (2) serial interface parameter symbol condition min. typ. max. unit shift clock cycle t cyk sck 900 ns high level shift clock pulse width t whk sck 400 ns low level shift clock pulse width t wlk sck 400 ns shift clock hold time t hstbk stb ? sck 1.5 m s data setup time t ds1 data ? sck - 100 ns data hold time t dh1 sck -? data 400 ns stb hold time t hkstb sck -? stb - 1 m s stb pulse width t wstb 1 m s wait time t wait 8th clk -? 1st clk 1 m s remark the typ. value is a reference value when t a = 25 c. (3) parallel interface (8-bit/4-bit) parameter symbol condition min. typ. max. unit enable cycle time t cyce e -? e - 900 ns high level enable pulse width t whe e 400 ns low level enable pulse width t wle e 400 ns stb pulse width t wstb 1 m s stb hold time t hkstb 1 m s enable hold time t hstbk 1.5 m s data setup time t ds2 d 0 to d 7 ? e - 100 ns data hold time t dh2 d 0 to d 7 ? e 300 ns remarks 1. the typ. value is a reference value when t a = 25 c. 2. in 4-bit parallel mode, d 0 to d 3 = l.
30 m m m m pd166 75 a switching characteristics waveforms ac measurement point v ih v il v oh v ol input output ac characteristics waveform osc t whc1 t wlc1 1/f osc t whc2 t wlc2 t f t r osc in osc bri serial interface (input) t ds1 t dh1 t whk t cyk t wstb t hstbk t hkstb stb sck data t wlk serial interface (output) sck data t phl t plh
31 m m m m pd166 75 a 8-bit parallel interface stb e d n t hstbk t wle t whe t cyce t dh2 t ds2 t wstb t wkstb 4-bit parallel interface stb e d n t hstbk t wle t whe t cyce t wait t dh2 t ds2 upper bit lower bit upper bit lower bit upper bit lower bit t wstb t wkstb reset t wre reset
32 m m m m pd166 75 a 10. package drawing standard tcp drawing ( m m m m pd16675an-051) d16675an -051 -201 japan p0.25 0.01 165 = 41.25 0.05 w0.125 0.02 21.1 0.3 (sr) 21.1 0.3 (sr) (44.4) (cut line) 23.2 23.2 27 63.949 0.08 p0.7 0.01 54 = 37.8 0.055 w0.35 0.02 (40) (cut line) 44 25 4 1.5 2.575 0.01 2 4 6.7 13.7 0.8 0.015 1 0.015 0.2 0.2 5 1 cu 1.5 2.575 0.01 1.981 0.03 (cut line) (3) (0.6) 4.75 0.03 (coating area) 0 - 4.6 (4)(cut line) 4.1 0.2(sr) 4.8 5 5.3 0.2 (sr) (9.5) (cut line) 12.95 13.7 14.45 (1.2) 0.1 (4.2) (8.3) (cut line) 8.8 polymide adhesive copper plating solder resist upilex-s epoxy electrolysis cu sn epoxy 75 m 12 m 25 m min 0.25 m 25 m this figure is shown by copper side over polyimide 5 sprocket holes (23.75 mm) for 1 pattern corner radius is 0.30 mm max. all tolerances unless otherwise specified 0.05 mm. (1.2) 17.68 a 2 22.125 (mark) 22.125 (mark) 3.3 0.2(sr) 3 1.4 0.1 6.7 (coating area) 0 - 4.6 6.81 specification max0.9 f
33 m m m m pd166 75 a standard tcp drawing ( m m m m pd16675an-051) detail of test pad 14.45 from p.c. p0.25 0.35 0.35 0.30 0.20 0.30 0.20 0.30 0.20 0.35 0.08 detail of a part 2- 1.3 pi hole 2- 1.1 cu hole 2- 1.9 cu ff f tape unwinding direction output leads unwinding direction face (copper)
34 m m m m pd166 75 a standard tcp drawing ( m m m m pd16675an-051) pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 dummy v lc5 dummy v lc4 v lc3 v lc2 dummy v lc1 v lcd v lcd amp in (-) amp in (+) amp out c 1 - c 1 - c 1 + c 1 + c 2 - c 2 - c 2 + c 2 + v dd2 vext osc bri osc in osc out da cha v dd1 v dd1 v cha v ss cs 0 cs 1 cs 2 reset d 7 /ns d 6 /cae d 5 d 4 d 3 d 2 d 1 d 0 /data e/sck stb v ss v ss ws v dd1 pocout clkout sync v ee v ee dummy dummy dummy com 16 com 15 com 14 com 13 com 12 com 11 com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com 1 pcom 1 seg 1 seg 2 seg 3 seg 4 seg 5 seg 6 seg 123 seg 124 seg 125 seg 126 seg 127 seg 128 com 17 com 18 com 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 com 32 pcom 2 dummy dummy
35 m m m m pd166 75 a notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m m m m pd166 75 a reference document number quality grades on necs semiconductor devices c11531e semiconductor device mounting technology manual c10535e the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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